Method of manufacturing amorphous-silicon thin-film transistors
US5091337A · kind A · utility
24Cited by
2References
3Claims
0Family size
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Key dates
| Filing date | Nov 1, 1990 |
| Grant date | Feb 25, 1992 |
| Priority date | — |
| Expiry date | Nov 1, 2010 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing an amorphous silicon thin film transistor in which a gate insulating layer is provided over a gate on a substrate. An amorphous silicon layer is formed on the gate insulating layer, and a protective insulating layer is formed on the amorphous silicon layer. A pattern conforming to the gate is applied to the protective layer, and the amorphous layer is exposed in regions outside of the pattern. A doped silicon layer is then added, and source and drain electrodes formed to partly overlap the remaining protective insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.