Self calibrating timing circuit
US5093584A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 1991 |
| Grant date | Mar 3, 1992 |
| Priority date | — |
| Expiry date | May 6, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00195
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock circuit, together with a control current generator and a ratio circuit coupled thereto. The ratio circuit, of the invention, utilizes at least two capacitors each of which is coupled in series with a respective transistor and arranged in parallel with one another. Each capacitor transistor transistor pair is in parallel to the other and coupled between the control current generator and ground so that at least one of the transistors in a selected capacitor transistor series can be selectively turned off while the other can be directly controlled by the clock cycle. This circuit, generates timing edges within a clock cycle which timing edges can be any fraction of the clock cycle, and comprises a clock, a controlled current generator, and a ratio circuit coupled to the clock and the generator. Preferably this ratio circuit comprises at least two capacitor-transistor pairs coupled in parallel between the generator and ground with the clock being coupled to the control electrode of one of the transistors and being coupled to the control electrode of the other transistor together with a turn-off signal source. An element for discharging the capacitors is included in the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.