Stacked-capacitor for a DRAM cell
US5095346A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 1990 |
| Grant date | Mar 10, 1992 |
| Priority date | — |
| Expiry date | Aug 31, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/318
Abstract
There is disclosed a stacked capacitor with high capacity which ensures structural stability in a DRAM cell and a method for manufacturing the same. The stacked-capacitor is of a hollow (or cylindrical) capacitor where both ends of several polysilicon layers which form a storage electrode are connected with each other. In construction, this inventive stacked-capacitor includes: a first polysilicon layer coupled to the source region so as to extend in parallel with surface of the substrate over the left and right sides of the source region; a bridge polysilicon layer, extending in the upward direction of the substrate from both ends of the first polysilicon layer; a dielectric film formed so as to contact with the surfaces of the bridge polysilicon layer, first polysilicon layer, second polysilicon layer; and a third polysilicon layer formed so as to contact with the surface of the dielectric film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.