Internally decoupled integrated circuit package
US5095402A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 1990 |
| Grant date | Mar 10, 1992 |
| Priority date | — |
| Expiry date | Oct 2, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A decoupling scheme is presented which is well suited for use with any type of integrated circuit package. In accordance with the present invention, a flat decoupling capacitor is attached directly to the top of an IC die and is electrically connected to the IC by means of raised conductive bumps provided either on the surface of the decoupling capacitor or on the IC die surface. These conductive bumps interconnect the internal electrodes of the capacitor to the power and ground circuits of the IC. The resulting decoupling scheme provides a decoupling loop with an inductance which is significantly lower than previously disclosed decoupling loops.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.