Semiconductor device and method of producing the same

US5098855A · kind A · utility

Assignee

• HITACHI, LTD. · JP

Inventors

• Kazuhiro Komori · Higashikurume, JP
• Kenichi Kuroda · Tokyo, JP
• June Sugiura · Musashino, JP

Key dates

• Filing date: Mar 28, 1990
• Grant date: Mar 24, 1992
• Expiry date: Mar 28, 2010

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S257/90

Abstract

Disclosed is a semiconductor integrated circuit device which includes first field effect transistors of a LDD structure having a floating gate as memory cells and second field effect transistors of the LDD structure as elements other than the memory cells, and which is used as EPROM. A shallow, low impurity concentration region of the first field effect transistor as a part of its source or drain region has a higher impurity concentration than a shallow, low impurity concentration region of the second field effect transistor as a part of its source or drain region.