Memory array with electrically programmable memory cells and electricaly unprogrammable, unerasable memory cells, both types of memory cells having floating gate transistors
US5099451A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 1988 |
| Grant date | Mar 24, 1992 |
| Priority date | — |
| Expiry date | Nov 16, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To avoid differentiation, in manufacture, between the random-access memory cells and read-only memory cells of the same memory array, the memory cells are all made by the same technology. These memory cells employ essentially floating gate transistors. The random-access memory cells are programmed, in a stand way, by injecting or not electronic charges in the floating gates of the transistors. The read-only memory cells are put in a programmed or an unprogrammed state by the selective implantation of impurities or not in the conduction channels of the floating gate transistors of these memory cells. There is an improved concealment of the content, which is designed to remain concealed, of these memory cells, at the same time, the conditions for making prototypes to order are improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.