Variable delay line phase-locked loop circuit synchronization system
US5101117A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 1991 |
| Grant date | Mar 31, 1992 |
| Priority date | — |
| Expiry date | Feb 22, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system for synchronizing the operation of a CPU and coprocessor operating from a common clock signal includes a first voltage controlled delay line connected to receive the clock signal and delay it by a fixed time interval before supplying it to one of the CPU or coprocessor. A second voltage controlled delay line is connected to receive the clock signal and delay it by an adjustable time interval before supplying it to the other of the CPU or coprocessor. The time interval of the second delay line is determined by the potential of a control signal generated from a phase locked loop circuit coupled to the output terminals of the CPU and coprocessor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.