Electrically programmable non-volatile memory device and manufacturing method thereof
US5101250A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 1990 |
| Grant date | Mar 31, 1992 |
| Priority date | — |
| Expiry date | Dec 20, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6893
Abstract
A 1-transistor type flash EEPROM is disclosed. The memory cell in the EEPROM includes a control gate formed on a silicon substrate with an insulating layer disposed between them, and a floating gate formed to extend over the upper face and one side face of the control electrode with an insulating layers disposed between them. Drain and source regions are created in the silicon substrate on the opposite sides of the control gate. The area in the silicon substrate under the control gate between the drain and source regions defines a channel region. In the EEPROM, an application of high-level voltage to the control gate and the drain region produces hot electrons in the vicinity of the opposite ends of the drain region which are driven into the floating gate across the insulating layer, causing the floating gate to store data-representing charge. The flash EEPROM has uniform characteristics among memory cells and reduced cell area for improved miniaturization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.