Method for improving device scalability of buried bit line flash EPROM devices having short reoxidation beaks and shallower junctions
US5102814A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 2, 1990 |
| Grant date | Apr 7, 1992 |
| Priority date | — |
| Expiry date | Nov 2, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0411
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for fabricating contactless electrically programmable and electrically erasable memory cells of the flash EPROM type. The cells use elongated source and drain regions disposed beneath field oxide regions. A high quality tunnel oxide is grown on the channel regions of the device, followed by deposition of a polysilicon buffer layer. The use of the polysilicon buffer layer results in short reoxidation beaks. The field oxide is grown in a short, low temperature wet oxidation step, enhanced by the presence of heavy dopant implants. The use of a short, low temperatue oxide growth allows the use of thin nitride masking members and results in short reoxidation beaks as well as less stress on the substrate during field oxide growth. Also, since a low temperature field oxidation is used, the quality of the tunnel oxide will be maintained. The thin nitride masking members are removed in a wet etch process which does not degrade the underlying polysilicon buffer layer. Therefore, the polysilicon buffer layer does not need to be removed and remains as part of the device. Since the polysilicon buffer layer is not removed, there is no damage to the underlying tunnel oxide, and this lay…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.