Semiconductor integrated circuit device having a gate array with a RAM and by-pass signal lines which interconnect a logic section and I/O unit circuit of the gate array
US5103282A · kind A · utility
11Cited by
8References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 10, 1990 |
| Grant date | Apr 7, 1992 |
| Priority date | — |
| Expiry date | Sep 10, 2010 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a gate array with a RAM, by-pass signal lines which interconnect a logic section and I/O unit circuit of the gate array are disposed so as to extend above the RAM. In order to minimize mutual interference, signal lines formed from a layer which is adjacent to the by-pass signal lines are disposed so as to intersect the latter at right angles. In addition, interconnection pitches in different layers which extend parallel with each other are set so that noises are cancelled in differential sense circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.