Event qualified testing protocols for integrated circuits
US5103450A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 12, 1991 |
| Grant date | Apr 7, 1992 |
| Priority date | — |
| Expiry date | Mar 12, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/86
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A set of event qualified test protocols for use in testing integrated circuits is disclosed. A boundary scan architecture for use in the integrated circuit (10) comprises input and output test registers (12,22) having functions controlled by an event qualifying module (EQM) (30). The EQM (30) receives a signal indicating a matching condition has been met. The EQM receives additional signals which indicate which testing protocol of the possible protocols is selected. The EQM (30) may control the input and output test registers (12,22) to perform a variety of tests on the incoming and outgoing data. During testing, the internal logic (20) may continue to operate at speed, thereby allowing the test circuitry to detect faults which would not otherwise be observable. A memory buffer (64) may be included to store a plurality of input data for test data. A set of standard protocols is disclosed which allows interoperability between EQMs on multiple IC's in a circuit. By adhering to a standard set of standard event qualification protocols, all IC designs produced with the boundary scan architecture will be capable of operating together to perform advanced test operations of the circuit is …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.