Low current semiconductor memory device
US5105384A · kind A · utility
18Cited by
6References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 6, 1988 |
| Grant date | Apr 14, 1992 |
| Priority date | — |
| Expiry date | Apr 6, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Each column latch circuit latches a potential of each bit line and that of each control gate line before information is written in a memory cell. Thus, so-called page mode writing can be performed. A column latch circuit comprises two inverters of the same polarity and statically latches an input potential. As a result, chip size can be reduced without any leakage of an electric charge representing information. Reduction of operating current requirements is also achieved by the use of inverters of the same polarity in combination with control of at least one transistor within each of the two inverters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.