Method for improving the electrical erase characteristics of floating gate memory cells by immediately depositing a protective polysilicon layer following growth of the tunnel or gate oxide
US5106772A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 9, 1990 |
| Grant date | Apr 21, 1992 |
| Priority date | — |
| Expiry date | Jan 9, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A method for fabricating floating gate memory arrays with improved electrical erase characteristics and a reduced gate oxide defect density is described. According to the invented method, a protective polysilicon layer is deposited immediately following growth of the tunnel or gate oxide. The polysilicon layer caps the gate oxide--protecting it from exposure to defect-causing contaminants and to insure that a uniform tunnel oxide thickness is maintained across the entire length of the channel; especially over the electron tunneling regions. Following application of the protective polysilicon layer, a second polysilicon layer is deposited and merges with the first polysilicon layer to form the floating gate for the device. Erase speed is improved for flash EEPROM devices fabricated according to the present invention by about 5-100 times.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.