Interconnect method for semiconductor devices
US5107321A · kind A · utility
24Cited by
12References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 2, 1990 |
| Grant date | Apr 21, 1992 |
| Priority date | — |
| Expiry date | Apr 2, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A BiCMOS device is revealed. The BiCMOS device achieves improved performance through the use of wrap-around silicide contacts, improved MOS gate formation, the use of n- and p-type LDD's, the formation of very shallow base regions in bipolar transistors, and through separate implants for base regions of the bipolar transistors and source/drains of the MOSFETS.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.