Stacked bit-line architecture for high density cross-point memory cell array
US5107459A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 1990 |
| Grant date | Apr 21, 1992 |
| Priority date | — |
| Expiry date | Apr 20, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A stacked bit-line architecture utilizing high density cross-point memory arrays forms a DRAM semiconductor memory device. The true and complementary bit-line pairs connected to the respective memory cell arrays are formed in two metal layers, one above the other. A bit-line interconnector region is provided that uses a third interconnection layer together with the first and second layers to transpose the vertical stacking of each pair and to transpose the planar alignment of adjacent bit-line pairs. The DRAM memory cell array has a high density cross-point memory cell architecture that behaves electrically as a folded bit-line array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.