Method of making a non-volatile memory cell utilizing polycrystalline silicon spacer tunnel region
US5108939A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 16, 1990 |
| Grant date | Apr 28, 1992 |
| Priority date | — |
| Expiry date | Oct 16, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and structure for forming in an EEPROM memory transistor a tunnel dielectric region having an extremely small surface area. A floating gate region is formed in the conventional manner above a gate dielectric layer. The drain region is exposed utilizing photolithographic techniques and the gate dielectric removed therefrom. A thin layer of tunnel dielectric is then formed on the exposed drain region. A thin layer of polycrystalline silicon is then formed and etched in order to create very narrow floating gate extensions of polycrystalline silicon along the edge of the previously formed floating gate. The floating gate extension formed in this manner which overlies the drain region is separated from the drain region by thin tunnel dielectric. A dielectric is then formed on the device in order to provide a dielectric over the drain region which has a greater thickness than the tunnel dielectric underlying the floating gate extension.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.