Michael J. Hart
73Patents
14h-index
60Co-inventors
87Inventor score
Filing activity: Oct 16, 1990 → Apr 20, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6777978B2 | Structures and methods for selectively applying a well bias to portions of a programmable device | Electricity | 87 | Expired |
| US6621325B2 | Structures and methods for selectively applying a well bias to portions of a programmable device | Electricity | 61 | Expired |
| US5108939A | Method of making a non-volatile memory cell utilizing polycrystalline silicon spacer tunnel region | Electricity | 52 | Expired |
| US5726484A | Multilayer amorphous silicon antifuse | Electricity | 37 | Expired |
| US5970372A | Method of forming multilayer amorphous silicon antifuse | Electricity | 33 | Expired |
| US6268639A | Electrostatic-discharge protection circuit | Emerging Cross-Sectional Technologies | 32 | Expired |
| US5293331A | High density EEPROM cell with tunnel oxide stripe | Electricity | 27 | Expired |
| US8299564B1 | Diffusion regions having different depths | Electricity | 26 | Active |
| US5455790A | High density EEPROM cell array which can selectively erase each byte of data in each row of the array | Emerging Cross-Sectional Technologies | 24 | Expired |
| US5870327A | Mixed mode RAM/ROM cell using antifuses | Physics | 19 | Expired |
| US7504854B1 | Regulating unused/inactive resources in programmable logic devices for static power reduction | Electricity | 18 | Active |
| US8261229B2 | Method and apparatus for interconnect layout in an integrated circuit | Electricity | 15 | Active |
| US9575111B1 | On chip detection of electrical overstress events | Electricity | 15 | Active |
| US6949951B1 | Integrated circuit multiplexer including transistors of more than one oxide thickness | Electricity | 15 | Expired |
| US6645802B1 | Method of forming a zener diode | Emerging Cross-Sectional Technologies | 14 | Expired |
| US6243294A | Memory architecture for non-volatile storage using gate breakdown structure in standard sub 0.35 micron process | Physics | 14 | Expired |
| US6549458B1 | Non-volatile memory array using gate breakdown structures | Physics | 14 | Expired |
| US6522582B1 | Non-volatile memory array using gate breakdown structures | Physics | 13 | Expired |
| US6982451B1 | Single event upset in SRAM cells in FPGAs with high resistivity gate structures | Electricity | 13 | Expired |
| US7109734B2 | Characterizing circuit performance by separating device and interconnect impact on signal delay | Physics | 12 | Expired |
| US7089527B2 | Structures and methods for selectively applying a well bias to portions of a programmable device | Electricity | 11 | Expired |
| US5786240A | Method for over-etching to improve voltage distribution | Emerging Cross-Sectional Technologies | 11 | Expired |
| US9281807B1 | Master-slave flip-flops and methods of implementing master-slave flip-flops in an integrated circuit | Electricity | 10 | Active |
| US6768335B1 | Integrated circuit multiplexer including transistors of more than one oxide thickness | Electricity | 10 | Expired |
| US10976239B1 | Systems and methods for determining polarization properties with high temporal bandwidth | Physics | 9 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.