Method and apparatus for the design and optimization of a balanced tree for clock distribution in computer integrated circuits
US5109168A · kind A · utility
32Cited by
5References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 27, 1991 |
| Grant date | Apr 28, 1992 |
| Priority date | — |
| Expiry date | Feb 27, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A balanced tree clock distribution network for an integrated circuit including a branching clock line of layered metal in which each branch of the clock line has equal resistance, apparatus for shielding the clock line on both sides in the same layer of material of the integrated circuit, and apparatus for providing jumpers for crossing the clock line at right angles in a different layer of material of the integrated circuit which jumpers apppear at the same preselected distances along each branch of the clock line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.