Multiple DRAM cells in a trench
US5109259A · kind A · utility
11Cited by
41References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 4, 1991 |
| Grant date | Apr 28, 1992 |
| Priority date | — |
| Expiry date | Feb 4, 2011 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/925
Abstract
A multiple DRAM cell trench structure provides increased cell capacitance. A deep trench (18) is formed in a P+ semiconductor substrate (10), with sufficient trench width to prevent the tapered trench sidewalls from pinching off at the bottom thereof. Plural memory cells are formed in the trench (18) to increase the cell density of the array. Field oxide strips (14, 15) are formed between conductive polysilicon bitlines (16, 38) and the P- substrate (12) to reduce capacitance and the soft error rate of the cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.