Method for producing an integrated circuit structure with a dense multilayer metallization pattern

US5109267A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Otto Koblinger · Ditzingen, DE
• Hans-Joachim Trumpp · Stuttgart, DE

Key dates

• Filing date: Jul 17, 1991
• Grant date: Apr 28, 1992
• Expiry date: Jul 17, 2011

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Disclosed is a method for manufacturing a high-denisty multilayer metallization pattern on an integrated circuit structure. Also disclosed are integrated circuit structures made with such method. The components of the integrated circuit may be formed on the substrate using conventional processes. A first metallization pattern is then formed on the semiconductor substrate having at least one integrated circuit. Next, the first layer of a double-layer insulation is applied over the first metallization pattern, and a photoresist layer is applied over the first layer for planarizing the topology of the metallization pattern and for defining a pad mask by a photoprocess over a conductive pad. For planarization of the topology, the photoresist layer and the first layer of the double-layer insulation are reactive ion etched at substantially the same rate to a desired depth. This reactive ion etching step also removes the first layer of the double-layer insulation from the pad mask area thereby exposing a metal pad. On top of the planarized topology, the second layer of the double-layer insulation is applied, and vias are opened in the layer by a plurality of dry-etching steps. The second …