Incorporation of dielectric layers in a semiconductor
US5110712A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 1990 |
| Grant date | May 5, 1992 |
| Priority date | — |
| Expiry date | Apr 25, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31138
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A system for integrating a composite dielectric layer in an integrated circuit to facilitate fabrication of a high density multi-level interconnect with external contacts. The composite dielectric layer comprises of a polymer layer which normally comprises a polyimide that is deposited using conventional spin-deposit techniques to form a planarized surface for deposition of an inorganic layer typically comprising silicon dioxide or silicon nitride. The inorganic layer is etched using standard photoresist techniques to form an inorganic mask for etching the polymer layer. A previously deposited inorganic layer functions as an etch stop to allow long over etches to achieve full external contacts which, in turn, allows high density interconnect systems on multiple levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.