Formation of composite monosilicon/polysilicon layer using reduced-temperature two-step silicon deposition
US5110757A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 1990 |
| Grant date | May 5, 1992 |
| Priority date | — |
| Expiry date | Dec 19, 2010 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/969
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A reduced-temperature two-step silicon deposition performed at different silicon sources is used in forming a composite monosilicon/polysilicon layer (20/24/26) on a body that contains a monosilicon region (10) and an adjoining dielectric regin (12). The first step entails selectively depositing silicon, preferably using dichlorosilane as a CVD silicon source, to grow a first monosilicon layer (20) on exposed monosilicon at an average body temperature less than or equal to 950.degree. C. Substantially no silicon accumulates on exposed dielectric material during the first step. The second step entails non-selectively depositing silicon, preferably using silane as a CVD silicon source, at an average body temperature less than or equal to 950.degree. C. to grow a second monosilicon layer (24) on the first monosilicon layer and to simultaneously grow a polysilicon layer (26) on the exposed dielectric material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.