Slow ramp high drive output pad
US5111064A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 5, 1990 |
| Grant date | May 5, 1992 |
| Priority date | — |
| Expiry date | Sep 5, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/164
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CMOS drive circuit an integrated circuit bonding pad is controlled by a pre-driver signals to change the potential on the output pad in accordance with these signals. Undesirable interference (emi) problems are eliminated or significantly reduced by slowing the ramp of change of the signal appearing on the output bonding pad when it changes from a high or positive binary state to a lower, relatively negative binary state. This is effected by splitting the output NMOS transistor of the CMOS output driver into two parallel connected, relatively small-sized transistor. Each of these transistors is driven from the signal input terminal through a relatively low current source which causes the gate capacitance to be slowly charged.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.