Method of forming planar vacuum microelectronic devices with self aligned anode
US5112436A · kind A · utility
40Cited by
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3Claims
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Key dates
| Filing date | Dec 24, 1990 |
| Grant date | May 12, 1992 |
| Priority date | — |
| Expiry date | Dec 24, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J21/105
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A method for forming on a substrate a microelectronic device having a first and second element. According to the method, a first conductive layer is deposited on the surface. Next, a cap material is deposited, then the first element and a first element cap are formed from the first conductive layer and the cap material respectively. A sacrificial material is conformally deposited, then a second conductive layer is conformally deposited. The second conductive layer is anisotropically etched to form the second element. Finally, the sacrificial material is anisotropically etched.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.