Virtual instruction cache system using length responsive decoded instruction shifting and merging with prefetch buffer outputs to fill instruction buffer
US5113515A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 1989 |
| Grant date | May 12, 1992 |
| Priority date | — |
| Expiry date | Feb 3, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3816
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction buffer of a high speed digital computer controls the flow of instruction stream to an instruction decoder. The buffer provides the decoder with nine bytes of sequential instruction stream. The instruction set used by the computer is of the variable length type, such that the decoder consumes a variable number of the instruction stream bytes, depending upon the type of instruction being decoded. As each instruction is consumed, a shifter removes the consumed bytes and repositions the remaining bytes into the lowest order positions. The byte positions left empty by the shifter are filled by instruction stream retrieved from one of a pair of prefetch buffers (IBEX, IBEX2) or from a virtual instruction cache. These prefetch buffers are arranged to hold the next two subsequent quadwords of instruction stream and provide the desired missing bytes. The IBEX prefetch buffer is filled from the instruction cache after being emptied, but prior to those particular bytes being requested to fill the instruction decoder. This two level prefetching allows the relatively slow process of cache access to be performed during noncritical time. The instruction decoder is not stalled, wait…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.