Method and apparatus for preventing recursion jeopardy
US5115506A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 1990 |
| Grant date | May 19, 1992 |
| Priority date | — |
| Expiry date | Jan 5, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/462
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor including unprime registers for use during normal operation, prime registers for use during interrupts, a normal register set for use during normal operation and conventional interrupt operations, an alternate register set for use during fast interrupt operations, and a memory stack. Three status bits are used to indicate that one or more fast interrupts have been initiated but not completed, that a fast interrupt is occurring but there are no other fast interrupts being processed, and that the CPU is currently processing a fast interrupt. These status bits indicate if there is a recursion jeopardy and are used to control the flow of information between the normal and alternate register sets and the memory stack in order to prevent recursion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.