Contact for integrated circuits
US5117273A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 1990 |
| Grant date | May 26, 1992 |
| Priority date | — |
| Expiry date | Nov 16, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a contact in a semiconductor integrated circuit includes the formation of a conformal oxide layer over the device followed by formation of a doped glass layer. The integrated circuit is heated to cause the glass layer to reflow, improving planarity of the circuit. A second conformal oxide layer is then formed, and contact vias are cut through the three part interlevel dielectric layer. Side walls are then formed in the via by depositing a third conformal layer, and anisotropically etching such layer. This isolates the doped reflowable glass layer from the via. Metal interconnect can then be deposited and defined, forming a contact in the via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.