Method for producing trench structures in silicon substrates for VLSI semiconductor circuits
US5118383A · kind A · utility
9Cited by
7References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 31, 1990 |
| Grant date | Jun 2, 1992 |
| Priority date | — |
| Expiry date | Dec 31, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3065
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for producing trench structures having vertical, smooth side walls and straight, flat trench floors in silicon substrates. The reactive ion etching is implemented in a triode single-wafer plate reactor upon use of an etching mask preferably composed of SiO.sub.2, and with an etching gas atmosphere exclusively composed of chlorine, being implemented at a low-pressure. Compared to known ion etching processes, the method provides acceptable etching rates with a carbon-free, simple etching chemistry. The method is particularly useful for producing DRAMs with cell concepts of more than 4 Mbits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.