System for selectively communicating instructions from memory locations simultaneously or from the same memory locations sequentially to plurality of processing
US5121502A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 1989 |
| Grant date | Jun 9, 1992 |
| Priority date | — |
| Expiry date | Dec 20, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A horizontal architecture computer in which a plurality of instructions are selectively communicated to a processing unit simultaneously or sequentially. The computer includes a processing unit with a plurality of processors, an instruction unit with a plurality of storage locations for storing instructions, and means for communicating the instructions to the processors. A first connection circuit provides a plurality of parallel communication channels between the storage locations and the processors and a second connection circuit provides a single serial communication channel between the storage locations and the processors. The first circuit is selected if a multioperation instruction is to be executed, otherwise the second circuit is selected instead.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.