Automatic circuit tester employing a three-dimensional switch-matrix layout
US5124638A · kind A · utility
19Cited by
7References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 22, 1991 |
| Grant date | Jun 23, 1992 |
| Priority date | — |
| Expiry date | Feb 22, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2834
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An automatic circuit tester (10) employs a scanner (20) embodied in a group of interconnected main scanner boards (46, 47) that provide switching by means of mechanical relays. In order to provide a cross-point matrix and structure without unacceptable stub lengths, the relays are mounted on auxiliary boards (114) that extend transversely from the surface of each main board (46, 47). The main scanner boards plug into a scanner bus (50) in such a manner as to permit them to connect or disconnect adjacent links (70A-H, 72A-H) in sequences of links in the scanner bus (50).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.