Compact SRAM cell layout
US5124774A · kind A · utility
18Cited by
4References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 19, 1990 |
| Grant date | Jun 23, 1992 |
| Priority date | — |
| Expiry date | Jul 19, 2010 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/904
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A compact cell design for a static random access memory cell is achieved. The cell has two transistors with gates substantially parallel to each other. One interconnect connects the gate of one transistor to an electrode of the other transistor. Another interconnect connects the gate of the other transistor to an electrode of the first transistor. The two gates and the two interconnects form substantially a rectangle. A power supply circiut line is disposed outside the rectangle. This line and the two interconnects are formed from one conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.