Inventor · Belmont, CA, US

Joseph Tzou

24Patents
10h-index
17Co-inventors
72Inventor score

Filing activity: Jan 12, 1990 → Sep 25, 2015

Most-cited inventions

PatentTitleAreaCited byStatus
US5656861A Self-aligning contact and interconnect structure Emerging Cross-Sectional Technologies 124 Expired
US7142477B1 Memory interface system and method for reducing cycle time of sequential read and write accesses using separate address and data buses Physics 47 Expired
US5168076A Method of fabricating a high resistance polysilicon load resistor Emerging Cross-Sectional Technologies 37 Expired
US5172211A High resistance Polysilicon load resistor Emerging Cross-Sectional Technologies 34 Expired
US5166771A Self-aligning contact and interconnect structure Electricity 31 Expired
US5483104A Self-aligning contact and interconnect structure Emerging Cross-Sectional Technologies 27 Expired
US7146454B1 Hiding refresh in 1T-SRAM architecture Physics 24 Expired
US5620919A Methods for fabricating integrated circuits including openings to transistor regions Electricity 19 Expired
US5124774A Compact SRAM cell layout Emerging Cross-Sectional Technologies 18 Expired
US7269772B1 Method and apparatus for built-in self-test (BIST) of integrated circuit device Physics 12 Expired
US7728619B1 Circuit and method for cascading programmable impedance matching in a multi-chip system Electricity 10 Active
US8149643B2 Memory device and method Physics 9 Active
US7403446B1 Single late-write for standard synchronous SRAMs Physics 7 Expired
US7684257B1 Area efficient and fast static random access memory circuit and method Physics 6 Active
US8527802B1 Memory device data latency circuits and methods Physics 6 Active
US7196925B1 Memory array with current limiting device for preventing particle induced latch-up Physics 6 Expired
US8705310B2 Access methods and circuits for memory devices having multiple banks Physics 4 Active
US8040164B2 Circuits and methods for programming integrated circuit input and output impedances Electricity 3 Active
US8095747B2 Memory system and method Physics 2 Active
US9666255B2 Access methods and circuits for memory devices having multiple banks Physics 1 Active
US9640237B1 Access methods and circuits for memory devices having multiple channels and multiple banks Physics 1 Active
US7719908B1 Memory having read disturb test mode Physics 1 Active
US8873264B1 Data forwarding circuits and methods for memory devices with write latency Physics 0 Active
US8358557B2 Memory device and method Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.