Plural level chip masking

US5126006A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• John Cronin · Jericho, US
• Paul A. Farrar · Bluffton, US
• Robert M. Geffken · Burlington, US
• William H. Guthrie · South Burlington, US
• Carter W. Kaanta · Colchester, US
• Rosemary A. Previti-Kelly · South Burlington, US
• James G. Ryan · Sandy Hook, US
• Ronald R. Uttecht · South Burlington, US
• Andrew J. Watts · Saint Johnsbury Center, US

Key dates

• Filing date: May 31, 1991
• Grant date: Jun 30, 1992
• Expiry date: May 31, 2011

Classification

• Technology area (CPC G): Physics
• CPC primary: G03F1/50
• WIPO field: Optics
• WIPO sector: Instruments

Abstract

A sequence of masking steps reduces the amount of transference of a workpiece among work stations and reduces certain tolerances required for mask alignment in the construction of integrated circuits, and a gray level mask suitable for photolithography. In the integrated circuit, masking layers are developed directly in a wafer for delineating vertical and horizontal portions of an electrically conductive path. The mask is constructed of a transparent glass substrate which supports plural levels of materials having different optical transmissivities. In the case of a mask employing only two of these levels, one level may be constructed of a glass made partially transmissive by substitution of silver ions in place of metal ions of alkali metal silicates employed in the construction of the glass. The second layer may be made opaque by construction of the layer of a metal such as chromium. Both the wafer and the mask are fabricated by a photoresist structure which is etched in specific regions by photolithographic masking to enable selective etching of exposed regions of the level of materials of differing optical transmissivities. Various etches are employed for selective etching of …