Sense amplifier for a memory device
US5126974A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 16, 1990 |
| Grant date | Jun 30, 1992 |
| Priority date | — |
| Expiry date | Jan 16, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A MOS transistor sense amplifier employs cross coupled positive feedback for the load circuit of a differential amplifier with an equalizing switch at the amplifier output, and preferably also at the input. This basis amplifier circuit may be repeated in stages. When stages are employed, it is desirable that the first stage employs current mirror loading of the differential amplifier to reduce the data delay. Data delay is further reduced by providing strong amplification during the sense portion of the read cycle with a preamplifier, which preamplifier has its amplification reduced, preferably to unity by being turned off, when the sense portion of the cycle is finished, and most preferably when the input and output data lines are directly connected independently of the preamplifier, so that the preamplifier may be completely turned off to lower power consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.