Integrated circuit
US5128738A · kind A · utility
6Cited by
1References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 16, 1991 |
| Grant date | Jul 7, 1992 |
| Priority date | — |
| Expiry date | May 16, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory cell with parallel gates is disclosed. The direction of the gates is desirably chosen to minimize lithographic astigmatic effects. Thus gates of comparatively uniform width are produced and predictability of transistor performance thereby improved. Another embodiment of the invention features a connetion between two conductive layers and a source/drain. The connection forms a node between one access transistor and one pull-down transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.