Arithmetic unit having multiple accumulators
US5128888A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 1990 |
| Grant date | Jul 7, 1992 |
| Priority date | — |
| Expiry date | Apr 2, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3884
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An arithmetic logic unit includes structure for calculating in at least two stages, this structure including substructure for calculating in each of the at least two stages at least partially at the same time and substructure for ensuring the substructure for calculating in each of the at least two stages performs only one calculation at a time. Accumulators that work with pipe stages of a floating point unit may form all of part of the calculating structure. A method of performing calculations includes the steps of separating the calculations into at least two stages and separately accumulating the results of the stages using at least two accumulators, one each accumulator for each calculation at each of the at least two stages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.