Thin film transistor having an improved gate structure and gate coverage by the gate dielectric
US5132745A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 1991 |
| Grant date | Jul 21, 1992 |
| Priority date | — |
| Expiry date | Sep 6, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6739
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A thin film transistor includes a two-layer gate metallization comprising a relatively thin first layer of a first conductor and a relatively thick second layer of a second conductor with the second conductor being capable of being etched with an etchant that produces substantially no etching of the first conductor layer. During device fabrication, the thick gate metallization layer (second conductor) is selectively etched until all of that material is removed in the openings in the mask. The thin lower layer (first conductor) is then etched with a minimum of etching into the substrate. The gate dielectric and subsequent layers deposited over this gate metallization have high integrity and highly reliable continuity because of the sloped nature of the gate metallization sidewalls, and because of the shallow gate metallization topography due to minimization of substrate etching during gate metallization patterning.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.