System for cache space allocation using selective addressing
US5132927A · kind A · utility
20Cited by
1References
4Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 9, 1990 |
| Grant date | Jul 21, 1992 |
| Priority date | — |
| Expiry date | Oct 9, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for folding the address space of a reserved segment of a high speed memory into a designated part of the address space of a cache memory included in the high speed memory. Folding information for distinguishing between cache entries that have been folded from reserved segments and those that normally map into a designated segment of the high speed memory is stored. The folding information is utilized to determine whether a cache miss occurs when the designated segment of the cache memory is accessed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.