Mechanism for improving the randomization of cache accesses utilizing abit-matrix multiplication permutation of cache addresses
US5133061A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 1990 |
| Grant date | Jul 21, 1992 |
| Priority date | — |
| Expiry date | Oct 11, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic computer system including a central processor and a hierarchical memory system having a large relatively low speed random access system memory and a small high speed set-associative cache memory including a data store section for storing lines of data from the system memory and a cache directory for indicating, by means of line identifier fields at any time, the lines of the system memory data currently resident in cache, is provided with a way to improve the distribution of data across the congruence classes within the cache. A mechanism is provided for performing a permutation operation on an M bit portion (X) of the system memory address, which permutation determines the congruence class into which the address will map. The permutation mechanism performs a bit-matrix multiplication of said M-bit address with an M.times.M matrix (where M is a real positive integer greater than 1) to produce a permuted M-bit address (X'). The directory controls utilize the permuted M-bit address (X') to determine the congruence class of any given memory access and automatically access the congruence class of the permuted address (X') subsequent to the permutation operation to determi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.