Kimming So
26Patents
14h-index
31Co-inventors
81Inventor score
Filing activity: Dec 24, 1984 → Aug 25, 2005
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5581734A | Multiprocessor system with shared cache and data input/output circuitry for transferring data amount greater than system bus capacity | Physics | 71 | Expired |
| US5584013A | Hierarchical cache arrangement wherein the replacement of an LRU entry in a second level cache is prevented when the cache entry is the only inclusive entry in the first level cache | Physics | 70 | Expired |
| US4774654A | Apparatus and method for prefetching subblocks from a low speed memory to a high speed memory of a memory hierarchy depending upon state of replacing bit in the low speed memory | Physics | 51 | Expired |
| US5530832A | System and method for practicing essential inclusion in a multiprocessor and cache hierarchy | Physics | 49 | Expired |
| US5133061A | Mechanism for improving the randomization of cache accesses utilizing abit-matrix multiplication permutation of cache addresses | Physics | 45 | Expired |
| US6944746B2 | RISC processor supporting one or more uninterruptible co-processors | Electricity | 44 | Expired |
| US6073211A | Method and system for memory updates within a multiprocessor data processing system | Physics | 39 | Expired |
| US5048018A | Debugging parallel programs by serialization | Physics | 37 | Expired |
| US5553253A | Correlation-based branch prediction in digital computers | Physics | 36 | Expired |
| US6957306B2 | System and method for controlling prefetching | Physics | 32 | Expired |
| US5694573A | Shared L2 support for inclusion property in split L1 data and instruction caches | Physics | 23 | Expired |
| US6963613B2 | Method of communicating between modules in a decoding system | Electricity | 21 | Expired |
| US5655103A | System and method for handling stale data in a multiprocessor system | Physics | 16 | Expired |
| US5897651A | Information handling system including a direct access set associative cache and method for accessing same | Physics | 16 | Expired |
| US5533189A | System and method for error correction code generation | Physics | 13 | Expired |
| US8356158B2 | Mini-translation lookaside buffer for use in memory translation | Physics | 6 | Active |
| US5692151A | High performance/low cost access hazard detection in pipelined cache controller using comparators with a width shorter than and independent of total width of memory address | Physics | 5 | Expired |
| US5699538A | Efficient firm consistency support mechanisms in an out-of-order execution superscaler multiprocessor | Physics | 5 | Expired |
| US7386646B2 | System and method for interrupt distribution in a multithread processor | Physics | 5 | Expired |
| US7617380B2 | System and method for synchronizing translation lookaside buffer access in a multithread processor | Physics | 4 | Expired |
| US8726292B2 | System and method for communication in a multithread processor | Physics | 2 | Active |
| US6931494B2 | System and method for directional prefetching | Physics | 2 | Expired |
| US7167954B2 | System and method for caching | Physics | 1 | Expired |
| US7711906B2 | System and method for caching | Physics | 0 | Active |
| US7627720B2 | System and method for directional prefetching | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.