MOS transistor isolation method
US5134089A · kind A · utility
17Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1991 |
| Grant date | Jul 28, 1992 |
| Priority date | — |
| Expiry date | Sep 30, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A series of oxide growth and etch-back operations is employed to form the isolation region of an MOS device (10). The series of operations forms an oxidation susceptible layer (14) into oxidation resistant areas (21) and oxidation susceptible areas (19) thereby confining the effects of a thermal oxidation procedure to the oxidation susceptible areas (19) of the MOS device (10). The thickness of both the oxidized (19) and non-oxidized regions (21) is reduced. Another oxidation is performed and the oxidized material (19, 21) is thinned.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.