Highly stable semiconductor memory with a small memory cell area
US5134581A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Oct 29, 1990 |
| Grant date | Jul 28, 1992 |
| Priority date | — |
| Expiry date | Oct 29, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/125
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In order to obtain a highly stable SRAM cell having a small cell area, a cell ratio R is set to be R=(W.sub.DEFF /L.sub.DEFF)/(W.sub.TEFF /L.sub.TEFF)<3 where L.sub.DEFF and W.sub.DEFF denote an effective channel length and an effective channel width of two driver MOSFETs 3 and 4 respectively, and L.sub.TEFF and W.sub.TEFF denote an effective channel length and an effective channel width of two transfer MOSFETs 5 and 6 respectively. Further, a maximum current I.sub.R flowing into the active loads MOSFETs 1 and 2 is set to be greater than a current I.sub.L (1.times.10.sup.-8 A) that flows into the driver MOSFET 5 when a threshold voltage is applied across the gate and the cource of the MOSFET 5. The pair of active load MOSFETs 1 and 2 are stacked on the driver MOSFETs 3 and 4 and on the transfer MOSFETs 5 and 6.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.