Process for producing a stacked capacitor of a dram cell
US5135883A · kind A · utility
48Cited by
3References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 14, 1990 |
| Grant date | Aug 4, 1992 |
| Priority date | — |
| Expiry date | Sep 14, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/714
Abstract
A stacked capacitor of the fin-like structure is provided wherein the plurality of polysilicon layers constituting the storage electrode are connected with each other in the sawtooth-like manner to overcome the structural instability of the fin-like structure. The polysilicon layers constituting the storage electrode are extended overlaying each other, so that the capacity of the capacitor in a highly integrated DRAM may be increased without increasing the area occupied by the capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.