Method of fabricating P-buried layers for PNP devices
US5137838A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 1991 |
| Grant date | Aug 11, 1992 |
| Priority date | — |
| Expiry date | Jun 5, 2011 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/058
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A P-type buried layer is described for use with planar, silicon, monolithic, epitaxial, PN junction-isolated transistors of PNP conductivity primarily for use in IC construction. The buried layer includes a high concentration of boron and gallium along with germanium, which is in sufficient concentration to inhibit impurity diffusion in the silicon epitaxial layer. This inhibition effect has been found to be sufficient to cause the combination of boron and gallium to act as slow diffusers. The result is that the performance of arsenic and antimony, in the creation of buried layers for NPN transistors. Thus, the performance of NPN transistors can be matched for PNP transistors. This means that an IC can be fabricated so that more nearly equal performance NPN and PNP transistors can be fabricated simultaneously in a common substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.