Inventor · San Jose, CA, US

Sheldon Aronowitz

77Patents
21h-index
48Co-inventors
88Inventor score

Filing activity: Jun 11, 1985 → Nov 13, 2007

Most-cited inventions

PatentTitleAreaCited byStatus
US6331468A Formation of integrated circuit structure using one or more silicon layers for implantation and out-diffusion in formation of defect-free source/drain regions and also for subsequent formation of silicon nitride spacers Electricity 269 Expired
US6087229A Composite semiconductor gate dielectrics Electricity 97 Expired
US5376560A Method for forming isolated semiconductor structures Emerging Cross-Sectional Technologies 69 Expired
US5837598A Diffusion barrier for polysilicon gate electrode of MOS device in integrated circuit structure, and method of making same Electricity 60 Expired
US6033998A Method of forming variable thickness gate dielectrics Electricity 58 Expired
US6566262B1 Method for creating self-aligned alloy capping layers for copper interconnect structures Electricity 58 Expired
US6989565B1 Memory device having an electron trapping layer in a high-K dielectric gate stack Electricity 49 Expired
US5723896A Integrated circuit structure with vertical isolation from single crystal substrate comprising isolation layer formed by implantation and annealing of noble gas atoms in substrate Electricity 47 Expired
US5312766A Method of providing lower contact resistance in MOS transistors Emerging Cross-Sectional Technologies 46 Expired
US5963801A Method of forming retrograde well structures and punch-through barriers using low energy implants Electricity 46 Expired
US6156620A Isolation trench in semiconductor substrate with nitrogen-containing barrier region, and process for forming same Electricity 46 Expired
US6303047A Low dielectric constant multiple carbon-containing silicon oxide dielectric material for use in integrated circuit structures, and method of making same Emerging Cross-Sectional Technologies 40 Expired
US5441900A CMOS latchup suppression by localized minority carrier lifetime reduction Emerging Cross-Sectional Technologies 38 Expired
US6413881B1 PROCESS FOR FORMING THIN GATE OXIDE WITH ENHANCED RELIABILITY BY NITRIDATION OF UPPER SURFACE OF GATE OF OXIDE TO FORM BARRIER OF NITROGEN ATOMS IN UPPER SURFACE REGION OF GATE OXIDE, AND RESULTING PRODUCT Electricity 37 Expired
US5296387A Method of providing lower contact resistance in MOS transistor structures Emerging Cross-Sectional Technologies 32 Expired
US5296386A Method of providing lower contact resistance in MOS transistor structures Emerging Cross-Sectional Technologies 31 Expired
US5877530A Formation of gradient doped profile region between channel region and heavily doped source/drain contact region of MOS device in integrated circuit structure using a re-entrant gate electrode and a higher dose drain implantation Electricity 29 Expired
US5585286A Implantation of a semiconductor substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant subsequently implanted into the substrate to form P- LDD region of a PMOS device Electricity 27 Expired
US5459085A Gate array layout to accommodate multi angle ion implantation Emerging Cross-Sectional Technologies 26 Expired
US5468974A Control and modification of dopant distribution and activation in polysilicon Emerging Cross-Sectional Technologies 25 Expired
US5571744A Defect free CMOS process Electricity 24 Expired
US5137838A Method of fabricating P-buried layers for PNP devices Emerging Cross-Sectional Technologies 20 Expired
US5384477A CMOS latchup suppression by localized minority carrier lifetime reduction Emerging Cross-Sectional Technologies 20 Expired
US6060375A Process for forming re-entrant geometry for gate electrode of integrated circuit structure Electricity 19 Expired
US5298435A Application of electronic properties of germanium to inhibit n-type or p-type diffusion in silicon Emerging Cross-Sectional Technologies 18 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.