Process for the manufacture of power-MOS semiconductor devices
US5141883A · kind A · utility
8Cited by
12References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 24, 1990 |
| Grant date | Aug 25, 1992 |
| Priority date | — |
| Expiry date | Dec 24, 2010 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/126
Abstract
A process for the manufacture of power-MOS semiconductor devices achieves high cell density by the use of self-aligning techniques and photographic exposure equipment of the stepper type. The process calls for definition and formation of the source by a complementary spacer technique and metallization of the source and gate contact areas by silicides after formation of spacers on the gate wall.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.