Semiconductor memory device having a stacked capacitor cell structure

US5142639A · kind A · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventors

• Yusuke Kohyama · Yokosuka, JP
• Shizuo Sawada · Yokohama, JP
• Toshiharu Watanabe · Minokamo, JP
• Kinuyo Kohyama · Kawasaki, JP

Key dates

• Filing date: May 17, 1991
• Grant date: Aug 25, 1992
• Expiry date: May 17, 2011

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/714

Abstract

In a stacked capacitor cell structure of a semiconductor memory device, the MIM (metal-insulator-metal) capacitor to be used as a transfer gate comprises at least a unit stack of a first insulation film, a lower capacitor electrode, a capacitor gate insulation film, an upper capacitor electrode, another capacitor gate insulation film and an extension of the lower capacitor electrode. Thus, the surface area of the lower capacitor electrode can be enlarged without increasing the plane area exclusively occupied by memory cells. Moreover, with such a configuration, since the surface area of the lower capacitor electrode can be augmented without increasing the film thickness of the electrode, the technical difficulties that the currently known methods of manufacturing semiconductor memory devices with a stacked capacitor cell structure encounter are effectively eliminated and consequently troubles such as short-circuited lower capacitor electrodes become non-existent.