Method and apparatus for page recall of data in an nonvolatile DRAM memory device
US5146431A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 1990 |
| Grant date | Sep 8, 1992 |
| Priority date | — |
| Expiry date | Sep 20, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a non-volatile DRAM (NVDRAM) memory device comprised of NVDRAM cells, each comprising a DRAM cell and an EEPROM cell, a method and apparatus for the page recall of data whereby the page recall start address may be specified by the user through the memory device's external control pins. A page of memory cells is defined as all of the memory cells connected to a single word line. During any recall operation, data are recalled from EEPROM to DRAM in only one memory cell per bit line. The externally specified page recall start address is input onto an external pad. It is then transmitted through an address selector circuit into the inputs of a counter circuit. The outputs of the counter circuit serve as the page recall start address, which reenters the address selector circuitry to be transmitted to address decoding circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.