Erase performance improvement via dual floating gate processing

US5147813A · kind A · utility

Assignee

• Intel Corporation · US

Inventor

• Been-Jon Woo · Saratoga, US

Key dates

• Filing date: Oct 29, 1991
• Grant date: Sep 15, 1992
• Expiry date: Oct 29, 2011

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/923

Abstract

A process for fabricating floating gates for electrically programmable and electrically erasable memory cells of the flash EPROM or EEPROM type. The floating gates are a three layer structure. The first layer of the floating gate is a thin polysilicon layer of approximately 300-500 .ANG. thickness. The second layer is a silicon dioxide layer of approximately 20-30 .ANG.. The third layer is polysilicon of approximately 1000-1500 .ANG. thickness. The third layer is doped by implantation of phosphorous. This dopant is driven through the oxide layer to dope the first, thin polysilicon layer in a separate diffusion step or in subsequent high temperature processing. The grain size of the first, thin polysilicon layer is small and uniform from gate to gate due to the thinness of this layer and its light doping. This reduces variations in threshold voltage from gate to gate due to variable polysilicon grain size and orientation. This in turn results in improved yield and cycling endurance.