Method and apparatus for simultaneously decoding three operands in a variable length instruction when one of the operands is also of variable length
US5148528A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 1989 |
| Grant date | Sep 15, 1992 |
| Priority date | — |
| Expiry date | Feb 3, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3838
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction decoder for a pipelined data processing unit simultaneously decodes two source specifiers and one destination specifier. All three of the specifiers can be register specifiers in which the specified operand is the content of a specified register. Any one of the specifiers can be a complex specifier designating an index register, a base register, and a displacement. Any one of the source specifiers can specify short literal data. Data for locating the two source operands and the destination operand are transmitted over parallel buses to an execution unit, so that most instructions are executed at a rate of one instruction per clock cycle. The complex specifier can have a variable length determined by its data type as well as its addressing mode. In particular, the complex specifier may specify a long length of extended immediate data that is received through the instruction buffer over a number of clock cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.